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Ordering number : ENN7349
CMOS IC
LC75010W
LC75010W Car Audio DSP
Overview
The LC75010W is a car audio DSP IC that integrates the signal processing required by car audio systems, A/D and D/A converters, volume control, and other functions on a single chip. It can implement a car audio system with a minimal number of external components.
* Supply Voltage and Package Specifications -- DSP core, A/D converter (digital block), D/A converter (digital block): 3.3 V -- A/D converter (analog block), D/A converter (analog block), volume control, crystal oscillator: 5V -- Package: 100-pin SQFP (14x14 mm)
Features
* Hardware Functions -- Analog source selector (BTL:1ch, OTL:3 ch) -- 20 bits A/D (2ch) -- 24 bits DSP (core, program memory, data memory) -- SIO (CCB I/F) (CCB is LSB first input.) -- 24 bits D/A (4ch) -- EVR (4ch) * Software Functions* (See Note.) -- Bass/Mid/Treb -- Bal/Fad -- Fixed equalizer (Front/Rear/separately controlled) -- Loudness control -- Hybrid volume -- Anti-hard clip -- Dedekind (Speaton**) Note *: Software specifications can be modified in response to user requests. * DSP Functions (24 fixed-point DSP) -- Program ROM -- 8k words -- Data RAM -- 896 words
Package Dimensions
unit: mm 3181C-SQFP100
[LC75010W]
16.0 0.5 14.0
75 76
51 50
100 1
(1.0) (1.4) 0.5 0.2
26 25
0.145
1.6max
0.1
* CCB is a registered trademark of Sanyo Electric Co., Ltd. * CCB is Sanyo's original bus format. All bus addresses are managed by Sanyo for this format. Note **: Speaton is a registered trademark of Dedekind R&D. Users who want to develop, manufacture, or sell electronic equipment that uses Dedekind functions must enter a separate contract with Dedekind R&D for the use of those functions.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N2103TN (OT) No. 7349-1/12
14.0
SANYO: SQFP100
16.0
LC75010W
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Supply voltage (A/D, D/A, volume, etc) Supply voltage (crystal oscillator) Symbol VDDmax1 VDDmax2 Pin name AVDD1, AVDD2, AVDD5, AVDD6, AVDD7, AVDD8, AVDD9, AVDD10, AVDD11, AVDD12 XVDD DVDD1, DVDD2, DVDD3, DVDD4, DVDD5, DVDD6, AVDD4 AINRP1, AINRN1, AINLP1, AINLN1, AINRP2,AINLP2, AINRP3, AINLP3, AINRP4, AINLP4, VFLI, VFRI, VRLI, VRRI TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7, TEST8, TEST9, TEST10, TEST13, TEST14, PWDB CL, CE, DI, RSTB, INTB (Conditions: Audio disabled operating state, Std. Board installation ; See note) DO 0 -40 -55 Ratings min -0.3 -0.3 -0.3 typ max +6.0 +6.0 +4.0 VDDmax1 + 0.3
(max +6.0 V)
Unit V V V
Supply voltage (DSP core block)(I/O I/F, PLL block) VDDmax3 Maximum input voltage (A/D, D/A, volume, etc) Maximum input voltage (DSP core block) (I/O I/F block) VIN1
-0.3
V
VIN2 VIN3
-0.3 -0.3
VDDmax3 + 0.3
(max +4.0 V)
V V mW mA C C
+6.0 830 6.0 85 125
Allowable power dissipation Maximum output current Operating temperature Storage temperature
Pdmax Io Topr Tstg
Note Std. board : 114.3 mm x 76.2 mm x 1.5 mm, material ; glass epoxy resin
Allowable Operating Ranges at Ta = -40 to +85C, VSSD = VSSA = 0 V
Parameter Supply voltage (analog block) Supply voltage (crystal oscillator) Supply voltage (digital block, PLL) Symbol AVDD5 XVDD5 DVDD3.3 VIHD VIHD1 VILD VILD1 Full-scale input level Crystal oscillator frequency * Pin name AVDD1, AVDD2, AVDD5, AVDD6, AVDD7, AVDD8, AVDD9, AVDD10, AVDD11, AVDD12 XVDD DVDD1, DVDD2, DVDD3, DVDD4, DVDD5, DVDD6, AVDD4 PWDB, INITB, TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7, TEST8, TEST9, TEST10, TEST13, TEST14 CL, CE, DI, RSTB PWDB, INITB, TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7, TEST8, TEST9, TEST10, TEST13, TEST14 CL, CE, DI, RSTB AINRP1, AINRN1, AINLP1, AINLN1, AINRP2, AINLP2, AINRP3, AINLP3, AINRP4, AINLP4 XIN, XOUT 16.9344 Ratings min +4.75 +4.75 +3.0 0.7 x DVDD3.3 0.7 x AVDD5 VSS VSS typ max +5.25 +5.25 +3.6 Unit V V V
High-level input voltage
DVDD3.3 AVDD5 0.3 x DVDD3.3 0.3 x AVDD5 0.4 x AVDD5
V V V V Vp-p MHz
Low-level input voltage
Note*: Consult with the manufacturer of the crystal oscillator element used to verify that the circuit constant values are appropriate for that crystal oscillator element before using this circuit.
No. N7349-2/12
LC75010W Electrical Characteristics in the Allowable Operating Ranges
Parameter Symbol Pin name PWDB, RSTB, INTB, CE, CL, DI, TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7, TEST8, TEST9, TEST10, TEST13, TEST14 PWDB, RSTB, INTB, CE, CL, DI, TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7, TEST8, TEST9, TEST10, TEST13, TEST14 BUSY, DO, TEST11, TEST12 (Microcontroller: 5 V) High-level output voltage Low-level output voltage Analog output level Reference voltage output VOH VOL VOUT Vref1 Vref2 Vref3 IAVDD5 BUSY, DO, TEST11, TEST12 (Microcontroller: 3.3 V) BUSY, DO, TEST11, TEST12 AOUT1, AOUT2, AOUT3, AOUT4 Vref1, Vref2, Vref3 (Conditions: Audio disabled operating state, Std. board installed ; See note) AVDD5 = XVDD5 = 5V, DVDD3.3 = 3.3 V (Conditions: Audio disabled operating state, Std. board installed ; See note) AVDD5 = XVDD5 = 5V, DVDD3.3 = 3.3 V (Conditions: Audio disabled operating state, Std. board installed ; See note) AVDD5 = XVDD5 = 5V, DVDD3.3 = 3.3 V (Conditions: Audio disabled operating state, Std. board installed ; See note) AVDD5 = XVDD5 = 5V, DVDD3.3 = 3.3 V 2.35 0.6 x AVDD5 2.5 2.65 -5 4.5 3.0 5.5 3.6 0.5 Ratings min typ max 5 Unit
High-level input current
IIH
A
Low-level input current
IIL
A V V V VP-P V
55
72
mA
IXVDD5 Current drain IDVDD3.3
5
7
mA
65
85
mA
Power dissipation
Pd
515
680
mW
Note Std. board : 114.3 mm x 76.2 mm x 1.5 mm, material : glass epoxy resin
LC75010W Analog Characteristics
Conditions: Analog system: 5 V, digital system: 3.3 V, fs: 44.1 kHz, signal frequency: 1 kHz, from the analog source selector input to the volume control circuit output. Measurement band: 10 Hz to 20 kHz, using the SANYO-specified DSP evaluation board. Test circuit: LC75010W external circuit structure with the DSP operating in through mode (4-bit shiftup), room temperature Test equipment: Audio analyzer (Rohde & Schwarz UPD)
Parameter S/N Dynamic range THD+N
Conditions A-weighted, Input conditions: 2 Vp-p A-weighted Input conditions: 1.5 Vp-p. See note.
Ratings min 85 85 -- typ 90 90 -86 max -- -- -80
Unit dB dB dB
Note: THD+N shows the optimal characteristics for an input (1.5 Vp-p) that is 3 dB lower than the full-scale input level.
CCB Timing
Parameter Data setup time Data hold time Clock low-level time Clock high-level time CE wait time CE setup time CE hold time Data latch change time Data output time Symbol tSU tHD tCL tCH tEL tES tEH tLC tDC tDH DO, CL DO, CE DI, CL DI, CL CL CL CE, CL CE, CL CE, CL Pin name Ratings min 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.35 typ max Unit s s s s s s s s s
No. N7349-3/12
LC75010W Pin Assignments
AVDD4 VCO PDO AVSS4 DVDD4 DVSS4 DVB2 BUSY PWDB RSTB CE CL DI DO INTB TEST11 DVSS5 DVDD5 TEST12 TEST13 TEST14 DVSS6 DVDD6 XIN XOUT
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
AVSS0 AVSS1 AVDD1 AVDD2 AVSS2 AVSS3 AVB1 DVSS1 DVDD1 TEST0 TEST1 TEST2 TEST3 TEST4 DVSS2 DVDD2 TEST5 TEST6 TEST7 TEST8 TEST9 TEST10 DVB1 DVSS3 DVDD3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
Vref1 AVSS12 AVDD12 AINRP1 Ars4 Ars3 AINRN1 AINRP4 AINRP3 AVSS11 AVDD11 AINRP2 AVDD9 AVSS9 Vref3 AINLP2 AVDD10 AVSS10 AINLP3 AINLP4 AINLN1 Als3 Als4 AINLP1 AVSS8 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
LC75010W (Top view)
AVDD8 VFLO VFLI AOUT1 VFRO VFRI AOUT2 AVSS7 AVDD7 Vref2 AVB2 NC NC AVSS6 AVDD6 AOUT3 VRLI VRLO AOUT4 VRRI VRRO AVSS5 AVDD5 XVDD XVSS
No. N7349-4/12
LC75010W Pin Functions
Pin No. 97 94 77 80 89 85 92 82 93 81 Pin name AINRP1 AINRN1 AINLP1 AINLN1 AINRP2 AINLP2 AINRP3 AINLP3 AINRP4 AINLP4 Input/Output (I/O) I I I I I I I I I I Analog BTL input (Rch +) Analog BTL input (Rch -) Analog BTL input (Lch +) Analog BTL input (Lch -) Analog OTL input1 (Rch +) Analog OTL input1 (Lch +) Analog OTL input2 (Rch +) Analog OTL input2 (Lch +) Analog OTL input3 (Rch +) Analog OTL input3 (Lch +) Standby mode (active low) Setting the PWDB pin to the low level sets the LC75010W to standby mode (also know as "power down mode"). In standby mode, the DSP system clock and the crystal oscillator are stopped and the whole LC75010W goes to the stopped state. This pin must be held at the high level during normal operation. Reset (active low) A reset is normally applied at power on, after recovering from a temporary power outage, and after returning from standby mode ("power down mode"). Interrupt (active low) (Software clip input (0/1)) Provides feedback control to the DSP to prevent clipping when an overflow occurs in the amplifier output. Test pin Test pin Test pin Test pin Test pin Test pin Test pin Test pin Test pin Test pin Test pin Test pin Test pin Test pin Test pin Crystal input (384 fs = 16.9344 MHz) (fs = 44.1 kHz) Crystal output VCO control Charge pump output CCB enable CCB clock Data in Data out CCB ready monitor Outputs the state of the DSP CCB receive buffer. A low-level output from the BUSY pin indicates that the buffer is empty. A high-level output indicates that command data is present in the receive buffer. Volume front Lch output Volume front Lch input Volume front Rch output Volume front Rch input Volume rear Lch output Volume rear Lch input Volume rear Rch output Volume rear Rch input Function
34
PWDB
I
35
RSTB
I
40 10 11 12 13 14 17 18 19 20 21 22 41 44 45 46 49 50 27 28 36 37 38 39
INTB TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 TEST10 TEST11 TEST12 TEST13 TEST14 XIN XOUT VCO PDO CE CL DI DO
I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O I O I I I O
33
BUSY
O
74 73 71 70 58 59 55 56
VFLO VFLI VFRO VFRI VRLO VRLI VRRO VRRI
O I O I O I O I
Continued on next page.
No. N7349-5/12
LC75010W
Continued from preceding page.
Pin No. 100 66 86 72 69 60 57 9 16 25 30 43 48 8 15 24 31 42 47 29 23 32 3 4 53 61 67 75 88 84 90 98 26 1 2 5 6 54 62 68 76 87 83 91 99 7 65 52 51 95 96 79 78 Pin name Vref1 Vref2 Vref3 AOUT1 AOUT2 AOUT3 AOUT4 DVDD1 DVDD2 DVDD3 DVDD4 DVDD5 DVDD6 DVSS1 DVSS2 DVSS3 DVSS4 DVSS5 DVSS6 AVSS4 DVB1 DVB2 AVDD1 AVDD2 AVDD5 AVDD6 AVDD7 AVDD8 AVDD9 AVDD10 AVDD11 AVDD12 AVDD4 AVSS0 AVSS1 AVSS2 AVSS3 AVSS5 AVSS6 AVSS7 AVSS8 AVSS9 AVSS10 AVSS11 AVSS12 AVB1 AVB2 XVDD XVSS Ars3 Ars4 Als3 Als4 O O O O Input/Output (I/O) Reference voltage Reference voltage Reference voltage Analog out 1 Analog out 2 Analog out 3 Analog out 4 Digital VDD (3.3 V) Digital VDD (3.3 V) Digital VDD (3.3 V) Digital VDD (3.3 V) Digital VDD (3.3 V) Digital VDD (3.3 V) Digital VSS Digital VSS Digital VSS Digital VSS Digital VSS Digital VSS Digital VSS Digital board GND Digital board GND Analog VDD (5 V) Analog VDD (5 V) Analog VDD (5 V) Analog VDD (5 V) Analog VDD (5 V) Analog VDD (5 V) Analog VDD (5 V) Analog VDD (5 V) Analog VDD (5 V) Analog VDD (5 V) Digital VDD (3.3 V) Analog VSS Analog VSS Analog VSS Analog VSS Analog VSS Analog VSS Analog VSS Analog VSS Analog VSS Analog VSS Analog VSS Analog VSS Analog Board GND Analog Board GND OSC VDD (5 V) OSC VSS Analog Rch source control Analog Rch source control Analog Lch source control Analog Lch source control Function
No. N7349-6/12
LC75010W Block Diagram
VFLO
(C 1F)
Als3 Als4 DSP CORE (24 bits)
R DAC (24 bits) L.P.F. Vref R L.P.F.
VFLI AOUT1 VFRO
(C 1F)
AINLP1 AINLN1 AINRP1 AINRN1 AINLP2 AINRP2 AINLP3 AINRP3 AINLP4 AINRP4 Analog source selector ADC (20 bits)
DAC (24 bits)
VFRI AOUT2
Vref VRLO
(C 1F)
ADC (20 bits)
Program ROM (8 kw)
DAC (24 bits)
R L.P.F.
VRLI AOUT3
Vref
VRRO
(C 1F)
Ars3 Ars4
DAC (24 bits)
R L.P.F.
VRRI AOUT4
Vref Data RAM (896W) DVDD 3.3 V
DVSS AVDD AVSS VCO PDO PLL VCO CCB 5V
VREF
XOUT
XIN
DI DO BUSY
RESB PWDB INTB TEST14-0
CE CL
No. N7349-7/12
LC75010W CCB Control System Timing and Data Format The LC75010W uses a CCB (Computer Control Bus) serial bus, which is a SANYO-developed bus format. The input serial data consists of a total of (8 + DI + C) bits. Here, the first 8 bits are the CCB address, the next DI bits are the data bits, and the last C bits are control bits. The output serial data consists of (8 + DO) bits. Here, the first 8 bits are the CCB address and the next DO bits are the output data bits. Serial data can be input or output after power has been applied, the crystal oscillator and PLL circuits have stabilized, and a reset has been applied. * Serial Data Input CL: Normally high
CE CL
tSU, tHD, tEL , tES , tEH 0.75s
tLC < 0.75 s tEH
tEL
tES
tSU
DI Internal Data
tHD B0 B1
B2
B3
A0
A1
A2
A3
DI1 DI2 DI3 DI4
DI24
C1
...
C24 tLC
CL: Normally low
CE CL
tEL
tES
tEH
tSU
DI Internal Data
B0
tHD B1
B2
B3
A0
A1
A2
A3
D11
D12 D13 D14
DI168
C2
...
C24 tLC
* Serial Data Output CL: Normally high
CE CL
tSU, tHD, tEL , tES , tEH 0.75s tEL tES
tDC, tDH < 0.35 s tEH
tSU
DI DO
tHD B0 B1
B2
B3
A0
A1
A2
A3 t DC
S1 ...
t DC
S8 DO1
ttDH
DO45 DO46 DO47 DO48
CL: Normally low
CE CL
t EL
tES
tEH
tSU
DI DO
B0
tHD B1
B2
B3
A0
A1
A2
A3 tDC
S1
tDC
... S8 DO
tDH
DO45 DO46 DO47 DO48
Note: Since the DO pin is an n-channel open-drain output, the data transition times (tDC and tDH) differ depending on the value of the pull-up resistor used.
No. N7349-8/12
LC75010W * Serial Data Timing CL: Normally high
CE
tCH tCL
VIH
VIL
CL
VIH VIL VIH VIH
VIH
VIL
VIH
DI
VIL
DO
tLC Old

tSU
tHD
VIL
tDC
tEL
tES
tEH tDH
Internal data latch
New
When CL is stopped at the high level
CL: Normally low
CE
tCH tCL
VIH
VIH

VIL VIH VIH
CL
VIH
DI
VIL
DO
tLC Old

tSU
tHD VIL
tDC
tDC
VIH
tEL
tES
VIL
VIL
VIL
tEH
tDH
Internal data latch
New
When CL is stopped at the low level
Reset Timing After power has been applied, and after crystal oscillator operation and PLL circuit operation have stabilized, a reset must be applied at the point that the Vref voltages (Vref1, Vref2, and Vref3) exceed the minimum level of 2.35 V. The reset period must be set up to include a period of at least 0.5 s during which the reset signal is held fixed at the low level. Audio processing (audio input/audio output) cannot be performed during the A/D converter calibration period (100 ms), which directly follows the reset. Note on Changes to the DSP Core Main Clock The LC75010W DSP core main clock can be switched by setting the TEST8 pin either low or high as shown below.
TEST8 Low (DVSS) High (DVDD 3.3) DSP core main clock (Crystal oscillator: 16.9344 MHz) 38.1024 MHz 40.2192 MHz
No. N7349-9/12
LC75010W Notes on Filter Coefficient Settings (precision of calculations) The IIR filter calculations are performed using 24-bit coefficients, 24-bit delay functions, 24 x 24 = 48-bit multiplications, and 48 + 48 = 48-bit additions. For certain values of the filter coefficients, the precision can become inadequate during the process of the filter calculation. Such errors can result in switching noise occurring when changing between different steps in the volume control. *: This problem can occur when setting the second-order IIR with filter coefficients having low characteristic frequencies (for example, the cutoff frequency or the center frequency). For example, switching noise will occur if the coefficients for a high-pass filter with a cutoff frequency of 25 Hz and a Q of 0.7 are set with FixEQ.) The following workaround can be effective if switching noise occurs due to second-order IIR filter coefficient settings. * Increase the characteristic frequency without changing the second-order characteristics, for example, increase the cutoff frequency from 25 Hz to 100 Hz. * Use the second-order characteristics as the first-order characteristics and define the coefficients for first-order characteristics.
* Serial Input Data Format Examples Example 1: Data format for the volume function
CCB Address (8 bits) bit 0 78
... ...
volume function data (24 bits) 31 32
DI23, DI24, C1, C2,
control data (24 bits) 55
... ... , C23, C24)MSB
LSB(B0, B1, ... , A3, DI1, DI2,
Example 2: Data format for 24-bit coefficient data (Total: 200 bits maximum)
CCB Address (8 bits) bit 0 78
, A3, DI1, DI2, ...
Coefficient data0 (24 bits) 31 32
Coefficient data1 (24 bits) 55 56
... ...
Coefficient address (24 bits) 150151
...
control data (16 bits) 175176 (8 bits) 191192 199
... C23, C24)MSB
LSB( B0, B1,...
DI168, C1, C2, ...
* Serial Output Data Format Example Example 1: CCB status register format (Total: 64 bits)
CCB Address CCB status (8 bits) bit0 78 (8 bits) 15 16
DO1, DO2, ... ...
Monitor data1 (24 bits) 39 40
...
Monitor data2 (24 bits) 63
... , DO47, DO48)MSB
LSB(B0, B1, ... , A3, S1, S2, S8,
No. N7349-10/12
BTL1R+ BTL1L+ OTL2L OTL3L BTL1L--
OTL1R BTL1R-OTL3R OTL2R
OTL1L
Unless indicated otherwise, capacitors shown as : 0.1F : 10F
+
1.5 nF
+++ +
1.5nF
+
+
+++
+
VDD(5 V)
+ +
Vref1 AVSS12 AVDD12 AINRP1 Ars4 Ars3 AINRN1 AINRP4 AINRP3 AVSS11 AVDD11 AINRP2 AVDD9 AVSS9 Vref3 AINLP2 AVDD10 AVSS10 AINLP3 AINLP4 AINLN1 Als3 Als4 AINLP1 AVSS8
+
AVDD(5 V) XVDD(5 V)
VSS
+
AVSS DVSS
Peripheral Circuit Example
VDD(3.3 V) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DVDD(3.3 V)
47H
+
FL
+ + R:1 k
LPF
C:1500 pF FR C:1500 pF
+
R:1 k
+
AMP RL
LC75010W
Top view
+
LC75010W
+ R:1 k +
C:1500 pF
RR C:1500 pF
+ R:1 k
Input high level (3.3 V)
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
AVSS0 AVSS1 AVDD1 AVDD2 AVSS2 AVSS3 AVB1 DVSS1 DVDD1 TEST0 TEST1 TEST2 TEST3 TEST4 DVSS2 DVDD2 TEST5 TEST6 TEST7 TEST8 TEST9 TEST10 DVB1 DVSS3 DVDD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
AVDD8 VFLO VFLI AOUT1 VFRO VFRI AOUT2 AVSS7 AVDD7 Vref2 AVB2 NC NC AVSS6 AVDD6 AOUT3 VRLI VRLO AOUT4 VRRI VRRO AVSS5 AVDD5 XVDD XVSS
Input high level (5 V)
AVDD4 VCO PDO AVSS4 DVDD4 DVSS4 DVB2 BUSY PWDB RSTB CE CL DI DO INTB TEST11 DVSS5 DVDD5 TEST12 TEST13 TEST14 DV SS6 DVDD6 XIN XOUT
16.9344 MHz 22 pF 22 pF DVSS DVDD(3.3 V)
10 k 10 k 220 0.1 F Microcontroller(5 V)
Microcontroller supply voltage(5 V) 10 k
XVDD(5 V) AVSS AVDD(5 V)
No. N7349-11/12
Note: The component values shown here are provided for reference only, and are not guaranteed for use in mass-produced end products. : Consult the manufacturer of the crystal element used to determine the values of the components used in the crystal oscillator circuit.
LC75010W
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of November, 2003. Specifications and information herein are subject to change without notice. PS No. N7349-12/12

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